Re: 250466 PCB curiousness

On 7/12/19 10:28 PM, smf wrote:
> On 11/07/2019 16:14, Gerrit Heitsch wrote:
>> SRAM doesn't care what you do with the address lines during a read,
> 
> It doesn't? AFAIK the memory is still organised in rows and columns, a
> read still opens a line and connects it to something that reads the line.

Yes, but reading doesn't change the state of a cell, you just read the 
state of the flipflop representing the cell. So, if VIC changes the 
adress lines mid cycle (which is what happens with the VSP bug), the 
SRAM doesn't care. It will supply VIC with the data the address lines 
select. If those change then different data will be supplied. VIC might 
read garbage, but the contents of the SRAM won't change.

Therefore, data corruption cannot happen as it does with DRAM.

If SRAM did care, you'd have a problem with the Color RAM. This one gets 
selected during VIC's part of the cycle before the address lines are 
stable. I found out while trying a 2114 clone that includes a latch for 
the address lines (*). It latches the address lines once /CS goes LOW. 
Use this SRAM in a C64 and you'll notice problems with the color on the 
screen while the CPU has no problem and tests the color RAM as OK. To 
make this SRAM work in a C64, you have to OR the /CS signal with /RAS.

(*) from eastern Europe, no idea why they added that latch.

  Gerrit