Den Wed, 10 Jul 2019 19:41:04 -0500 skrev Jim Brain <brain_at_jbrain.com>: > On 7/10/2019 1:06 PM, Michał Pleban wrote: > > Jim Brain wrote: > > > > > > But the 6509 does have a SYNC pin, and I thought you have used it? > > It's the 6502 I used, and the code went through so many revisions, it > got hidden. Yep. I do use it. > > > But, the idea of a state machine like the Verilog uses still would > work. > > Sync or not, the state machine for the entire opcode matrix would be > large, probably too large for a CPLD. And, if you're doing an FPGA, > might as well just replace the CPU with the FPGA. How big does the state machine have to be though? Many 6502 instructions are similar enough to be able to share the same state thing if the goal is only to detect what is instruction fetches and what is data cycles. You really only need to sort the instructions in groups of different length, except those where the cycle count depends on the data processed. Btw, another (albeit a bit strange) solution would be to have a state machine that only detects if the CPU has crashed, and if so enables the MMU registers and does a reset. That way the MMU registers can be hidden and when you want to access them, you just execute one of the illegal instructions that crashes the CPU. Afaik when the CPU is crashed, it reads the same address over and over again until it sees a reset pulse. (Side track: at least on a PAL VIC 20, you can actually see the colors change slightly to a more blue-ish tone when the CPU has crashed (!!!) ). -- (\_/) Copy the bunny to your mails to help (O.o) him achieve world domination. (> <) Come join the dark side. /_|_\ We have cookies.Received on 2020-05-29 22:27:44
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