Re: C64 MMU POC

On 2019-07-08 09:44, Mia Magnusson wrote:

> A good thing about the C128 MMU is that it has two sets of registers.
> One full set that sits in the general I/O area, and a smaller set that
> sits in the $FFxx range (iirc). That way you can do a limited set of
> operations even when the full register set is invisible.

This business of partial access sounds like an unwelcome compromise, 
made necessary by the lack of some unused addresses to which the new MMU 
registers can respond.  So, what if the new MMU registers are made to 
respond to unused *opcodes* instead?  In other words, don't use memory 
mapped IO for the new registers.  Create some new instructions.

There are lots of unused opcodes, including several which are followed 
by an 8-bit operand which the CPU ignores but our MMU hardware could 
easily capture.  The logic for this is surprisingly simple once you get 
used to the idea.

6510 has a special problem, though.  With no SYNC pin, we'd need an 
alternative means of knowing when an opcode is being fetched.

Clever ideas, anyone?  I have two so-so (not great) solutions in mind, 
but I won't bother explaining just now.  Besides, maybe someone can come 
up with something better.

  -- Jeff