Re: C64 MMU POC

On 9/23/2019 12:30 AM, Kajtár Zsolt wrote:
> -----BEGIN PGP SIGNED MESSAGE-----
> Hash: SHA256
>
>> As I look at the MMU PLA mappings, it seems like the following
>> combinations will be prevalent:
>>
>> * ROMs banked in, IO banked in, so $cxxx is a good choice
>>
>> * ROMs out, IO in, so $cxxx is good, and so if $fxxx
>>
>> *All RAM, in which case $fxxx is best.
> Put them in RAM space and make it mappable just like any page. The knock
> sequence would just change alter the map so it becomes accessible. To make
> it complicated it's location could be part of the sequence.

I was already thinking of making it relocatable, but I can't put it in 
Virtual RAM space (or you could lose access to it if you unmap that page 
:-)  Still, I know what you mean and that's probably what I'll do.  It 
looks like the same setup can be adapted to the +4 and C16, and maybe 
even the 128, though not sure about the last one.

Still, I'll worry about this last, in lieu of testing other things.  As 
of tonight, with the addition of a 50Mhz oscillator,

* memory access between MMU mapping RAM and regular SRAM is handled (MMU 
SRAM is accessed in the first 41nS after RAS and CAS both go low, and 
Main SRAM is accessed for the remainder of the RAS/CAS cycle).

* MMU RAM is mapped into main address space at $c01x (low 8 data bits) 
for read and write

* MMU can be enabled or disabled ($c000:0)

*MMU mapping is working

* MMU window config (which map to update) is working ($c001)

* MMU map config (256 values) is working ($c002)


I spent a few hours running the VSP Lb code, and all looks good. Need to 
find a nice stress memory tester.

Things yet to do:


* Add in support to update high order bits on MMU RAM

* Add in write protect functionality (bit 15 of MMU mapping)

* Add IRQ trigger on page writes if enabled per page (bit 14 of MMU mapping)

* Consider whether I should reloc zp and stack in addition to the 
current relo of page 0 (0-fff)

* Create new design for 8 IC 64s and spin a PCB

Jim