Re: In search of bad 4164, 41256 DRAM

On Fri, Sep 20, 2019 at 7:55 PM Jeffrey Birt <birt_j_at_soigeneris.com> wrote:
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> I have this working well now for 4164 and 41256 devices. When not testing all pins connected to the DUT are set to HI-Z and power +5V is disconnected. This was done so chips can be removed inserted with the Arduino powered.
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> I was thinking of adding some 100ohm resistors in the address and control signal path as a simple protection against short circuits in the DUT. The program manages about 200kHz speeds (up to 380kHz if I get rid of a layer of abstraction) so I don’t think the added RC constant would be an issue. I'm worried about how the 4116 part might short internally. Shorts from -5V or 12V to ground or +5V would best be detected before powering up, I think. Maybe having a separate circuit that is connected before power is applied that looks for shorts from the power rails to each pin. Hopefully it is not possible to only find a short with the device under power and when trying to address a certain cell? Any thoughts?

resistor in series to address lines to the DRAMs where always (as far
as I know) used on 4116 and 4164 based systems. Usually 33 to 68 ohm
in series on each address line going to all the RAMs. This was done
probably to limit the transient current since usually each address
line went to at least 8 (or 16, even 24 and 32) chips. So your 100 ohm
to a single address line should be really not slowing down the
accesses at all.
I have seen a few 4116 shorting all the  supplies to ground when
missing the -5V supply with the others present.
A common failure mode is the data I/O pins shorted to a power rail or
not going to high impedance when the chip isn't addressed. So you must
take care not to blow the driver pin to the data Input of the chip.

HTH
Frank IZ8DWF
> Jeff Birt
>
>
> -----Original Message-----
> From: Gerrit Heitsch <gerrit_at_laosinh.s.bawue.de>
> Sent: Tuesday, September 17, 2019 1:51 PM
> To: cbm-hackers_at_musoftware.de
> Subject: Re: In search of bad 4164, 41256 DRAM
>
> On 9/17/19 8:40 PM, Jeffrey Birt wrote:
> > In doing some simple tests on one of the subject DRAM chips, a 41256 64kbit variant made by Motorola (MCM6256P15) I have come up with some surprising results.
> >
> > I can fill all 64kbits with 1 or 0, turn off the refresh and wait 30 seconds, then verify all cells and only come up with 100~700 incorrect bits. If the time without refresh is only 1 second only 1~2 bits will be wrong. I'm sure that if these tests were repeated with specific patterns of bits that more wrong bit values would be detected.
>
> Years ago I read an article where they tested DRAMs from different makers (that was in the 64Kbit and 256Kbit time). They found out that most US made DRAMs stuck very close to the datasheet, meaning don't give them their 128 (or 256) refresh cycles in 2ms (4ms) and they would lose data while the japanese made DRAMs would mostly retain the data for seconds without bit flips.
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> I thought it shows the different approaches. 'Good enough' and 'best we can make it'.
>
>   Gerrit
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