Re: In search of bad 4164, 41256 DRAM

On 17/09/2019 09:32, Gerrit Heitsch wrote:
>
> It should be since at power on the capacitor in a DRAM cell is empty
> and if you stop refreshing it, it will also become empty after a
> while. Whether this 'empty' is read as '1' or '0' depends on the
> location on the die and on the manufacturer.

Can you explain why empty is read as 1 or 0 though? As far as I know
dram cells are either empty or full and it checks if the cell is half
full to work out the 0 or 1. So unless they randomly put inverters in
there, an empty cell is an empty cell.

My thought was that during power on the dram is going to be unstable &
it could generate the pattern if the dram did the equivalent of a
refresh and the read part of it was done when there wasn't enough power
to accurately determine the cell is empty enough while the write was
done as the power stabilised. Maybe the power up ends up triggering a
write without a read.

The placement/layout would then make the difference purely because of
things like how much power was leaking around the chip.