Hi and lots of CBM/retrocomp related fun in 2020 to all! :-) We've got the next proto boards in Dec and we went on testing it on all possible combinations of boards and VICs we could put our hands on. Everything went fine until the Reloaded Mk-II [*]. Everything looked good at first but running test programs designed for imposing lots of activity of CPU, VASYL (the core chip on the board) and VIC showed some random glitches, leading eventually to a full crash. As we still have debug headers on this proto we wired (in VHDL :-) out a couple of debug signals, checking which out swhowed that we're occasionally getting phantom clocks, which we don't experience at all when using any of the CBM designed boards. This led us to believe that there must be something "different" with clocks the "Reloaded" board supplies. And – oh boy – the DOTCLOCK (the one that matters for what we do) certainly is different there than what I would expect it to be: https://www.dropbox.com/s/kxuh2lkyqyqlmxa/2020-01-02_140548_reloaded_mkii.png the ringing shots amplitude alone can exceed 2Vpp, effectively triggering false edge detection on occasions. Adding a small RC on the VICs end, both elements variable, allowed me to form the clock shape into something usable in the sense that no false edges appear anymore but - yeah - SISO: https://www.dropbox.com/s/gnsqu3qgfnis5oc/capture_2020-01-02_145854_reloaded_mkii_rc.png It seems to work and I could probably live with it but maybe someone has a better idea on how to "fix" that clock without deforming/attenuating it so much at the same time? I was thinking about clipping the tops/bottoms (tops alone would probably do the trick) with fast diodes, maybe? Any advices? * - BTW, does anyone have Mk-I and would be willing to lend it for testing? -- SD!Received on 2020-05-30 00:04:00
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