On Fri, 25 Aug 2000, Nicolas Welte wrote: > > My bet is that it's the "test mode" bit of the $d030 register (or was it > > $d02f)? That bit normally disables all VIC-IIe interrupts and blanks the > > You won the bet :-) But I'm also not sure if it's d02f or d030, I always > forget. I did say, "Or maybe it's a completely different hack of the VIC-IIe's implementation." But Marko edited it out ;) > Anyway, it would be very interesting to know more about that test bit. I am > not sure if the RAM refresh is corrupted if the test bit is set, because > raster lines are skipped completely, so the refresh counter probably also > gets affected. Good point. This would be more noticeable on some machines than others, hence it would be difficult to say what is an acceptable use of this feature and what is not. You'd have to make decisions about the maximum RAM refresh periods of *all* the different DRAM chips in C64s out there... Richard -- Richard Atkinson Software Engineer Tenison Technology EDA Ltd http://www.tenisontech.com/ - This message was sent through the cbm-hackers mailing list. To unsubscribe: echo unsubscribe | mail cbm-hackers-request@dot.tcm.hut.fi.
Archive generated by hypermail 2.1.1.