Am 19. April 2020 21:09:24 schrieb Gerrit Heitsch <gerrit_at_laosinh.s.bawue.de>: > On 4/19/20 8:53 PM, André Fachat wrote: >> >> So say you have a 4MHz capable SRAM, every second cycle could be used for >> the second CPU, and the other cycles would be used by the CPU and VIC. > > No... only the CPU has the AEC pin. VIC does not. It keeps it's address > lines offline during the CPU part of the cycle, but during its own cycle > it hogs the bus and you cannot take it off. Also, VIC multiplexes its > addresses internally, you cannot affect that timing. If you use SRAM you need to demultiplex the VIC address lines anyway. So demuxers can emulate the AEC for the VIC. > > So, unless you want to REALLY redesign the whole system, you can only > use the CPU part of the cycle and split it. And even that needs quite a > bit of changes to the system. Using SRAM seems to be the way to go with access speed as well as VIC AEC. I consider this quite a bit of change though as you say. André > > GerritReceived on 2020-05-30 01:32:28
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