Rainer Buchty wrote > On Tue, 2 Jun 2020, > silverdr_at_.org > wrote: > >> Thank you. We're considering the options we have at hand and the most >> probable one is that we shall move this register to $3e as simple >> shifting of the range by one or two is not feasible. This means we'll >> have to drop the plans we had for $3e/$3f but hey, you can't have >> everything (where would you put it?), can you? ;-) > > If you want to free the $d03x range, maybe an approach similar to the > mode registers of the 2681 DUART is suitable. > > Right now, you spell out DLIST and ADR0/1 as 16-bit registers, directly > accessible as LSB/MSB. To my understanding of the register description > (which might be wrong, of course) those addresses however only become > valid with subsequent strobing accesses, either to DLSTROBE (for DLIST, > that also can be triggered by the next occuring frame) or to PORTx (for > ADR0/1). > [snip] Hi Rainer, Thank you for having a careful look at the register set and for your suggestions. Unfortunately, in a multiprocessing environment of C64/BeamRacer implementing them could be counterproductive. For example, both ports are often used concurrently, one by the CPU, one by VASYL, without any need to arbitrate access. The ports can also execute independent writes to local RAM during the same system clock cycle, increasing overall performance. Putting them in a shared address range would negate both of these benefits. Additionally, being able to quickly update just one of the DLIST[LH] bytes is useful in some programming patterns we have discovered during the year of experimenting with VASYL. Again, sincere thanks for taking the time to investigate the documentation. We are working on expanding it with more advanced examples, helping to better communicate the depth of the architecture. Milek -- Sent from: http://cbm-hackers.2304266.n4.nabble.com/Received on 2020-06-07 01:00:03
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