>> Has anyone actually experienced the issue described by Gideon? Could the >> fact that we are pulling down just the RDY (as opposed to RDY and AEC he had >> to manipulate jointly with the DMA line) have any significance? > On 2020-06-13, at 09:55, Frank Wolf <webmaster_at_frank-wolf.org> wrote: > > The timings of 8500 compared to 6510 are slightly different. 8500 (or 850x) are slightly faster. > > AEC has no influence on the RDY# line (or vice versa)... it just tri-states R/W#, D0-D7, A0-A15. > In other words: If you want to control the data/Address bus you need to pull it too. In generic case yes. What we do on the BeamRacer requires finer granularity though. When seen from the EXPANSION port there's _DMA line, which combines the signals and does what you say. When seen from the VIC side, we have BA and AEC, which can be used to achieve the desired timing granularity. We haven't experienced any problems so far, even if conditions outlined in Gideon's document are met. Therefore the question - "where's the catch?" -- SD!Received on 2020-06-13 12:00:02
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