So, Tokafondo, if I'm understanding this correctly, your _immediate_ concern is to get data in and out of a 16-bit-wide peripheral IC, with "it would be nice if my 16-bit 65816 could physically do 16-bit I/O" happening to wander across your train of thought's tracks as you went. That's not a new or unusual procedure. You were pretty close with your "handle the data access as two simultaneous 8-bit accesses" plan -- that is indeed how it's done, except that the part where you try to juggle reading half of the device _directly_ is way more trouble than you need to go to. The basic method is this: 1. on your 65xx CPU, hook up a 6520 PIA or any of its more complicated brothers (VIA, CIA...). 2. Take 16 I/O lines from the IA chip and run them into the data pins of your 16-bit memory chip. 3. Hook up the read/write lines as necessary so that you can trigger data movement betwixt IA chip & memory chip as needed. 4. To read the 16-bit device, do whatever you arranged in step 3 to read its data into the two 8-bit Peripheral Data Registers of the IA chip, then read those individually into your 65xx as per normal. Writing to the 16-bit device is the same in reverse. > On Oct 12, 2020, at 2:03 PM, tokafondo <tokafondo_at_gmail.com> wrote: > > That's the thing... trying to talk to a 16 bit memory chip by splitting the > 16 bit data between the actual data bus and the 8 bits parallel port. > > My theory is: > > - Wire the MSB of the 16 bit RAM chip data bus to the parallel port of a PIA > like the W65C21. > - Wire the LSB of the 16 bit RAM chip data bus to the data bus of the 65816. > - Wire the 65816 address bus as usual, to the address buses of the other > chips. > > So when wanting to write a value to the 16bit RAM chip, the programmer would > first put the MSB in the parallel port, and then write the LSB to the memory > location. > > This last write would enable the /CS and /WE lines of the 16bit RAM chip, > that would already have present the MSB value in its MSB lines thru the > parallel port. > > *BUT* I don't know if the parallel port would had the MSB value there, > latched until a new value would replace the existing one, or if the parallel > port would discard the MSB value after a while. > > > > -- > Sent from: http://cbm-hackers.2304266.n4.nabble.com/ >Received on 2020-10-13 03:00:02
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