Re: FPGA using Python language

>     On 02/22/2021 1:55 PM admin_at_wavestarinteractive.com admin_at_wavestarinteractive.com <admin@wavestarinteractive.com> wrote:
> 
> 
>     Good points to add to what I just mentioned about a complete toolchain to go from HDL to a binary that you can load into a programmable logic device (FPGA for example). You key process is known as synthesis (for those that don't know) but also that simulation steps that you mentioned. 
> 
>     In theory, I can use Forth and create a HDL syntax but all that is meaningless until I can convert the source syntax into a proper logic binary for a particular FPGA and like you mentioned, there is those steps of simulation and the synthesis part. 
> 
Note: This is not really aimed for those who actually works on FPGA engineering.

There a multiple parts to synthesis but one important stage is called "Place and Route" and all this is important to create the binary file called a "bitstream". 

I am not sure how using Python as the language syntax for a hardware description because Python doesn't natively have such syntax. Verilog and VHDL are custom languages with a special syntax for describing hardware logic. There is a whole set of tools and processes before a core is created. A core (IP core) is (depending on conversational context) the hardware "source code" (the stuff used ultimately to create the bitstream file for a particular FPGA) or the bitstream file or both... which is a block of logic/data that makes an FPGA or ASIC work. When we are talking about what gets loaded into the FPGA itself, we are talking about the bitstream file. What you use as "source code" can be HDL code or even special visual logic-description scripts, etc.)… whatever that is.... a specialized tool chain (for FPGAs, ASICs, and other PLDs) is needed to synthesize the "source" stuff to the bitstream file needed for the FPGA.