On 6/1/2021 6:24 PM, smf wrote: > By my rough calculation that slows the cpu down to 1mhz 42% of the time > & 0mhz 8% of the time (on reads and writes). While IIRC Supercpu has > full speed reads and a write fifo. The write fifo is only 1 byte, so you only get the benefit of the FIFO once every 20 SuperCPU cycles, assuming no VIC cycle stealing. Again, keep in mind the OP's request. Pushing the VIC-II RAM off the main bus provides significant value for little cost, unless the app is video consumptive, in which case there was no point to push the VIC-II off the bus in the first place. A few TTL ICs to buffer the busses and stretch the clock is well within most hobbyists. Time slicing SRAM access to VIC and CPU requires significantly more logic (data latches for reads, logic to know when to use them, etc.) and I think is well above the OP's current request.Received on 2021-06-02 02:01:02
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