FWIW, I've ran LFT's VSP test program (separate program into first side of Lunatico demo) and I was never able to trigger the bug on any of my PAL machines (250407A, 250425, 2x 250469D). Frank On Wed, Jun 2, 2021 at 7:43 PM smf <smf_at_null.net> wrote: > > "Finally, this phenomenon hinges on the exact timing of the RAS signal at the nanosecond level, and on many machines the critical situation simply doesn't occur. The timing (and thus the probability of a crash) depends on factors such as temperature, VIC revision, parasitic capacitance and resistance of the traces on the motherboard, power supply ripple and interference with other parts of the machine such as the phase of the colour carrier with respect to the dotclock. The latter is assigned randomly at power-on, by the way, which could be the reason why a power-cycle sometimes helps. > > This is lft signing off. " > > > I'm not sure there is any easy way to tell. > > > On 02/06/2021 18:28, silverdr_at_wfmh.org.pl wrote: > > TOH it can change between power cycles so who knows what factors affect it. > > From how I understand how it works (address lines changing too close to /RAS going LOW), it would be a combination of VIC and RAMs and maybe clock jitter. Plus, of course, temperature. > > True. I am not looking for an exact recipe but am trying to increase my probability of finding a machine / combination of components which would expose the error at least somewhat repeatably.Received on 2021-06-03 11:00:02
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