As far as I'm aware, as long as (1) all of your chips are meant to operate at 5 V, and (2) they really are all various sorts of MOS as opposed to plain TTL, then you shouldn't have any issues. Even if only one (or neither) point is true, you can often still make it work safely by carefully checking the data sheets. Adding hardware buffers in between everything might protect them from _some_ types of voltage stresses, but the extra delays that would add - however small - would take any part of a circuit that was already pushing the timing tolerances a bit from "working" to "there's nothing WRONG, why is it dead?" In that scenario, you'd have to do all sorts of fudgery re: clock skew and the data sheet timing parameters ANYWAY. tl;dr: Check your plans against the data sheets. G. > On Nov 3, 2021, at 3:31 PM, Claudio Sánchez <tokafondo_at_gmail.com> wrote: > > I'm planning in doing some expermiments by using my C64 (as I call it, "cost reduced") chips and a couple of WDC's 6502 and 65816 chips I have. > > But before breaking something and having in mind all the voltage stuff, I'd like to know if I can interface directly the chips between them, even being from different xMOS types (NMOS, HMOS, CMOS). > > Or should I put extra components between them? > > Thanks all. >Received on 2021-11-09 17:00:12
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