Hello Gerrit, * On Thu, Mar 24, 2022 at 10:04:11PM +0100 Gerrit Heitsch wrote: > On 3/24/22 21:45, Spiro Trikaliotis wrote: > The NOP only makes sense if there is something happening inside the 177x > that needs a bit of extra time to finish before the next access to whatever > register can happen. There is, as I wrote in my first posting. The 6502 absolute addressing is as follows (looking into the MOS 6502 programming manual, appendix E.3): Clock Adress Bus PC DAta bus comments Cycle 1 PC PC + 1 OP CODE fetch op code 2 PC + 1 PC + 2 ADL fetch ADL 3 PC + 2 PC + 3 ADH fetch ADH 4 ADH,ADL PC + 3 Data fetch Data 5 PC + 3 PC + 4 OP CODE fetch new op code, execute old op cod So, if I start an access to the WD177x status register at an PC with A0=A1=0, then A0=A1=1 will end in clock cycle 5. The CPU will try to force these values of A0 and A1. So, I just accessed the WD177x at address $xxx0 (or ...4 or ...8 or ...C), and the values might be changed (even for a very short time) to $xxx3 (or ...7 or ... B or ...F - you get it). So, there would be a very short access to the WD177x data register. Unfortunately, accessing the data register has a side effect: On reading, the WD177x will "think" that the data read from the floppy has been read, and it will not signal this again. Thus, a read routine will miss one byte! On writing, the WD177x will "think" that there is new data in the register, thus, it would not ask for a new byte until that byte is written to disk. If the code makes sure that the LDA/STA never starts on an address with A0=A1=0, this will not happen. On other addresses, in clock cycle 4, A0=A1=0, and in cycle 5, either A0 or A1 will still be 0. Thus, there will not be any "11" glitch (with A0=A1=1) in this case. Yes, I know, this is still a guess, but I think this makes much more sense now than before. Regards, Spiro -- Spiro R. Trikaliotis https://spiro.trikaliotis.net/Received on 2022-03-24 23:00:23
Archive generated by hypermail 2.3.0.