El 30/03/2022 a las 12:57, Julian Perry escribió: > Hello Claudio, > > Wednesday, March 30, 2022, 10:40:33 PM, you wrote: > > *>> Claudio Sánchez - Tokafondo wrote on 30.03.2022 13:11: > >>>> So why not to get rid of the CIAs and make both CPUs to access the same memory location inside the computer, via DMA? > >>> If you get rid of the CIAs, you are really no longer compatible with the 1541 and its descendants. So if you wish go this route, why not get rid of the second CPU altogether and make something like the CBM-II low cost drives which were driven by the computer's CPU? > >> I thought the only thing the CIAs were doing was serializing the >> parallel data put into its registers by the CPUs. > >> My theory was that by bypassing that 'serialization', the very same >> set of commands sent to the drive could be used. > > *My understanding of the 1541/2040/4040 at least is that direct access to the R/W head is simply not possible: the only access is via the byte-wise shift register, ported access being via one of the two 6522 CIA's. The reason for that, rather odd method being that variable clocking being possible to provide the different bit densities/zones required. As it is, bit-banging would be tricky to do. Of course, with the MFM formats, that has to be externally handled. Ok, let me explain. My understanding of the logical blocks of the CBM drives is: |=====================| |==========| =============== | CIA DOING | ================ | CPU | ============== |=======| serial bus | PARALLEL <-> SERIAL | SYSTEM BUS | RAM | HEAD CONTROL | HEADS | =============== | CONVERSION | ================ | ROM | ============== |=======| |=====================| |==========| So the CIA does NOTHING when controlling the heads. Just gets and sends data to the serial bus. > /-- > Best regards, > Julian /mailto:jp_at_digitaltapestries.com <mailto:jp@digitaltapestries.com>Received on 2022-03-30 17:00:03
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