I thought I had commented the transistor schematic as to how it 'worked'. I will double-check myself tomorrow... This is pretty much 8 parallel shift registers each consisting of 8 bits. The registers can be preloaded. Each chain of registers can be shortened from 8 bits and there is the usual "end around shift" with an xor gate. Dave On Sat, 31 Dec 2022, 22:00 Jim Brain, <brain_at_jbrain.com> wrote: > On 12/31/2022 5:11 AM, David Roberts wrote: > > Not to my knowledge. > > > > But the schematics are on my Google drive and it is a very simple > circuit. > I thought it might be a neat evening exercise, but I wasn't sure where > the schematic was on the list of docs. I saw the actual transistor > logic in a PDF, but that's a bit low level to easily convert to > Verilog/VHDL. > > > > You will not end up with the volatile nature of the 6702 if you slow > > the clock down - but who cares? > > > > The correct implementation of the 6702 was embedded into VICE. > > Maybe that's an easier path fo HDL conversion. > > Jim > >Received on 2023-01-01 00:02:50
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