Re: MOS 8500 CPU for C64C

From: silverdr_at_srebrnysen.com
Date: Wed, 30 Aug 2023 17:27:10 +0000
Message-Id: <7FA4BB4B-2773-42A9-8F58-4B152EFCFDB1_at_srebrnysen.com>
> On 30 Aug 2023, at 15:31, Gerrit Heitsch <gerrit_at_laosinh.s.bawue.de> wrote:
> 
>>>>>>> I know the 8500 CPU for the cost reduced C64C is rare would anyone here
>>>>>>> have any extras I could get?
>>>>>> 
>>>>>> You can also use a 6510 from an older C64, they are compatible.
>>>>> Just the HMOS(II) vs NMOS apply to those two, right?
>>>> 
>>>> Yes, the only difference is the process. I have seen 250425 boards with 8500 CPUs.
>>> 
>>> Yeah, /me too. And I know they're functinally the same but as we know CSG did various things with the numbering like marking the HMOS CIAs with NMOS number. Although doing it the other way around (like putting 8500 on a 6510) would make even less sense I guess ;-)
>> FWIW, 8500 vs 6510 can be detected in software by checking how many
>> cycles it takes for the unconnected port bits to decay from 1 to 0
>> level when the DDR is switched from output to input.
>> I made a test ASM for proof of concept years ago. The decay time is
>> also temperature dependent, but the 8500 is some (binary) order of
>> magnitude slower due to probably much better gate insulation and lower
>> die temperature (gate leakage depends on temperature).
> 
> I remember a thread about that a few years ago and the outcome there was that it's not reliable, the best 6510 are better than the worst 8500. So you can only output a probability.

Do I understand correctly that the results _partially_ overlap? Something like:

|=======6510=======|
               |======8500=====|

If yes, then it would be possible to properly "binarily" determine the variant on both sides of the overlapping range? Of course sample size might be an issue for reliable derivation of the boundaries for each variant

Or is the overlap different?

-- 
SD!
Received on 2023-08-30 20:00:02

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