16550 (808X BUS) interfacing to 6XXX bus (Was: Re: The ROR bug - seems it wasn't a bug after all.)

From: Jim Brain <brain_at_jbrain.com>
Date: Mon, 12 Feb 2024 13:24:31 -0600
Message-ID: <01da31ce-594e-43c7-b178-447537dcfef5_at_jbrain.com>
On 2/12/2024 10:50 AM, Ethan Dicks wrote:
> On Mon, Feb 12, 2024 at 10:39 AM A. Fachat <afachat_at_gmx.de> wrote:
>>>> I know the 6551 has ... problems ...
>>> I'd try to hook up a 16550 to a 6502 if I needed a UART for a new design.
>> The 16550 is my default actually for many years now.
> Are there any design "gotchas" that have to be considered (funny
> timing stuff with Phi2 or stretching any timing signals) or do you
> just plumb data bus and select to it?  I know the Z8530 has some
> software timing issues (because you select a register with the first
> write then use the register with the next access there's internal set
> up time) but I wouldn't expect that from the 16550.
>
> I've used them in x86 machines and I'd just like to learn if there are
> any issues to be aware with connecting them to 65xx machines.

At least for the 8250 and the derivatives/upgrades (16550 being one), 
just gate WR and RD with PHI2, as Andre did here:

http://www.6502.org/users/andre/icaphw/c64ser.html

RESET has to be inverted, and IRQ as well, and IRQ is not wired-or, so a 
diode or dedicated input is needed for it (or an OC inverter)

Jim
Received on 2024-02-12 21:00:04

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