Hola, On Mon, 7 May 101 g.baltissen@hccnet.nl wrote: > Hallo Per, > > > Agreed. On a 500 MHz CPU you'll get a maximum of about 500 instruc- > > tions per interrrupt, and the the interrupt latency including context > > switch is usually somewhere between 200-300 cycles, iirc. > > I was thinking about a 486-66. Seems we can forget the idea for the moment. > But within 5 years these 500-machines will be available for pennies, I hope > :) I got curious, so I've been looking at the instruction timings at http://www.quantasm.com/opcode_i.html Sure enough, a number of instructions are down at the 1 cycle level. But others are in the 10s of cycles (still a vast improvement over the 8088 timings I vaguely remembered). The INT opcode seems to take a lot more cycles in protected mode, and IRET takes 8-27 cycles. So perhaps 50-100 cycles for interrupt overhead? So it looks to me like there's time for anywhere between 10 to maybe 250 instructions per interrupt, on a 500MHz machine (500 cycles/interrupt). Dunno what your interrupt routine will do, but if there are N cycles left over at the end, that leaves N MHz for the "non-interrupt" code to run at; having a 50MHz or 100MHz machine for the other stuff doesn't seem too bad to me (certainly if windows isn't running). -Steve - This message was sent through the cbm-hackers mailing list. To unsubscribe: echo unsubscribe | mail cbm-hackers-request@dot.tml.hut.fi.
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