[Marko M_kel_] writes:
>But I clearly remember that there were 2 or 3 accesses to $01xx.
If I could remember where I put the results of my logic-analyser
experiments, I'd repost them. From memory, reset looks just like a normal
interrupt response, with R/W high. The data that would have been written
was still driven onto the data bus (despite it not being a write cycle)
>Does anyone have good ideas why the 6502 ignores its RDY input during
>write cycles?
My best guess is that if RDY was active during writes, you'd have R/W low
and the data bus driven while you're trying to do your DMA. But that's
a pretty weak theory.
John
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