A thought just occurred to me...
should /could the ispLattice device be programmed as a generic DMA handler
so that various projects can benefit from the component? I can think of
several applications that would love to avoid handfulls of TTL chips
* Marko's REU clone
* Ruud's PC card
* my core accelerator ideas and a 64HDD Ramlink equivalent....
If there was a standard 65xx DMA chip specification then it could become the
"glue" for many other people's ideas also.. and would save on some
re-invention work. The REC chips is hard to find, and I know I wouldn't be
experimenting with any spares in existance....
Just a thought, I have no CPLD experience....
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