> > You start by making a component instantiation of an entity you
> > haven't defined yet.
>
> That's not the problem. More problematic would be that I forgot to put the
> component description into a package... So the component/end component
> should be enclosed in package/end package.
>
I'll try encapsulating them in a package and see if that makes the
syntax
checker happy, but if that was your intent shouldn't you have included
a port mapping?
I can't see that it makes a difference if the component is declared
first
as long as the dangling references are resolved eventually, but I don't
know
what VHDL wants.
Or maybe the syntax checker is just stupid.
> > I think you've got too many elseif's in the "DMA transfer" (?) ie
> >
> > if rst='0' then
> > elsif rising'edge(dotclk) then
> > elsif falling'edge(dotclk) then
>
> No, why? Some actions happen with the rising edge, others with the falling
> edge.
I wasn't quibbling with the way you were doing it, just trying to figure
out
how you meant to express it.
Syntactically, the problem is (the syntax checker says) you haven't
closed
all your ifs.
> > I don't think there's any such thing as too many comments.
>
> Usually I'd agree - but I think the signal names are pretty much
> self-explaining if you are familiar with the REC registers.
That's your first real mistake ;)
(not that your wrong..)
bogax
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