ncoplin_at_orbeng.com
Date: 2002-04-17 06:05:29
Hello Gideon,
>The people that also read the "CommodoreOne" message board probably already
>know that some time ago I started implementing a 6502 core and a 6510
I'm glad you posted it here also!!
>PS. Milestone one has been reached... let's look forward to the second: a
>6502/6510 with sdram, and to further 'releases' of the 32-bit version!
I've always wondered about this so hopefully someone knows the answer. If
the address and data was stored in a tri-state latch connected to the bus at
the 6510 socket, and the clocking signal allowed to pass though.... would
the address read or write occur for each cycle available (ie use "ready" and
"clock" to enable the address output).
I ask this because a socket processor upgrade needs to write to the
mainboard's RAM and IO, regardless of how much of its own RAM it has. The
mainboard RAM access is controlled by the VIC so timing is fixed to 1us.
- Nick
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