From: Gideon Zweijtzer (gideonz_at_dds.nl)
Date: 2002-04-30 09:33:07
>>What about the 6509? That is a 6502 with the difference that it has
>>4 more address lines. The output values of the 4 address bits is
>>determined by the values of register 0 and 1. register 1 is used for
>>the data load and store operations in the lda (),y and sta (),y
>>opcodes and reg. 0 otherwise. (r0/r1 maybe vice versa, but in principle
>>that is it).
>
>This chip is indeed and interesting one. The theme could be extended to
>include a full 8-bit paging offset, allowing 16MB rather than 1MB access.
>For the setting of the register one of the illegal fatal codes
>could be used
>as the operand.
Please wait for a few more days, until I release the details of the CPU I am
making. It will be completely 32 bit, so even the 16 MB barrier will not be
there. And YES, of course the new CPU is code compatible with the 6502,
except for the illegal opcodes, because I need space for mapping 16 and 32
bit opcodes in the map.
Gideon
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