From: Gideon Zweijtzer (gideonz_at_dds.nl)
Date: 2002-06-24 13:16:59
|Gideon Zweijtzer wrote:
|> If anyone is planning to do so, please note that generating a huge truth
|> table for VHDL or verilog is a lot easier than trying to find the logic
|> formula's yourself. Then run the VHDL or verilog to a compiler / fitter
for
|> a PLD and there you'll be able to find your equations.
|
|Are we talking about the same thing? We already know the truth table
|(the states of the output lines for any given combination of input line
|states) for the C128 PLA. This information is not in a very useable
|format for any other purpose than (perhaps) copying the logic equations
|to a chip. The chip doesn't care how readable the equations are to a
|human; in fact, as far as I understand, they do not allow the formulae
|to be nested very deeply.
Yes we are talking about the same thing. I am just trying to hint to a way
to obtain elegant equations from a truth table. If you would read out the
PLD like an EPROM, just the way you and others did it, and generate VHDL
code from it, you will get something like this, using your 3-bit in 1-bit
out example:
case inputvector is
when "000" => outputvector <= '0';
when "001" => outputvector <= '0';
when "010" => outputvector <= '1';
-- ... etc
end case;
When you compile this into a PLD, the program that does this compile and
fitting step will produce the optimized equations for you. Whether you use
the PLD or not doesn't matter; it's the equations that count. That's the
whole point I was trying to make :)
If you want to improve readability, you can replace the words inputvector
and outputvector to a set of signal names that are actually used on the
Commodore board.
Gideon
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