From: Michael Huth (520052975648-0001_at_t-online.de)
Date: 2002-10-02 13:21:51
Hello,
a friend and I built some interface for c64 / c128 to connect it to
external hardware.
By testing the part for serial transfer with two c64 connected, we figured
out that loading TimerA with $0001 (i.e. 250kbaud) produced often bit
errors. ($0002 worked well)
There were also errors when connecting two CIA with a very short cable.
The strange thing is, the number of bits transferred is always right.
Though in the bit stream seem to occur some shifts. ($01 to $02 or $01 to
$80 f.e.)
A related interesting fact is, that there is a 8 second copy between two
1571 drives. So it seems to be possible to archieve 250kbaud with 2Mhz
clocked CIA (and TimerA $0002).
So what's wrong when loading TimerA with $0001 , the CNT signal seems to be
ok. (btw: CNT seems to be the same signal like TimerA output at PB6 in
toggle mode)
Are the bit errors some chip bug?
Another question:
The SDR is very easy to handle for transferring complete bytes. So if there
occurs some bit shift the receiver and sender shift registers are not
running synchronous anymore.
How do I re-align the shift registers to the byte-borders ?
(means I want that the shift register is at position 0 after it shifted 8
bits out, if there is some bit shift in the bit stream, one shift register
might stop at position 1 (other at 0). How do I get it set to position 0
again?)
I found no docu that describes this case.
The two (untested) ideas I have is
-toggling the SDR in/output flag in CRA.
-reading SDR of receiver after x<8 bits are shifted in
Ciao...
...Micha
Message was sent through the cbm-hackers mailing list
Archive generated by hypermail 2.1.4.