From: Spiro Trikaliotis (trik-news_at_gmx.de)
Date: 2002-12-10 08:14:23
Hello Nick,
Nick Coplin wrote:
> >at least the HCT types (74HCT4049, 74HCT4050), although I never tested it.
>
> My only worry about this method is that if my objective of using a CPLD (36
> or 72 macrocell device) is to reduce chip count, then it is all kind of
> defeated by having to buffer the outputs.... Some Xilinx chips were 5V
> originally, but the supply I was to go through only sells 3.3V
> boards/chips.....
I see your point. Anyway, IIRC, TTL as used in the CBMs needs at least 3.1 V
for recognizing a high voltage, and I think there's not much room between
3.1 V and 3.3 V to recognize it deterministically. It might help to use
a Vcc a little bit higher than 3.3V (3.4V or 3.5V), but I'm not sure, and
I'm not sure what impacts this would have on the life cycle of the chips.
Using transistors to drive the 5V wouldn't help either, would it? ;-)
Spiro.
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