levente_at_terrasoft.hu
Date: 2002-12-10 09:45:28
Guys!,
On Tuesday 10 December 2002 05:42, ncoplin@orbeng.com wrote:
> >>Seems most new LSI technology is going to 3.3V designs (eg CPLDs etc).
> ...
There shouldn't be any problems when coupling 3.3V CMOS outputs to CBM MOS
style NMOS inputs.
- The CMOS output HIGH level is (if not loaded) theoretically the supply
voltage.
- The load, when driving an NMOS input, is low.
- Finally, these NMOS inputs are TTL level compatible -- thus, they
identify anything above 2.6 volts as HIGH. (And anything below 0.8V as LOW).
3.3v output vs. TTL input is a lucky situation, the chips can be coupled
directly, without any interfacing logic.
(If the inputs would be 5V CMOS, then you would be in trouble; CMOS
compares logical levels vs its supply voltage. at 5v, LOW would be below
1.65V, HIGH above 3.3V).
Best regards,
L.
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