From: Rainer Buchty (buchty_at_cs.tum.edu)
Date: 2003-08-19 01:37:15
> Hmmm, the problem is that i´d really want to start development as soon as
> possible (since it´s gonna be a vacation project), so i don´t have much time
> for both building the accelerator and learning VHDL...
VHDL is not that hard to learn. If you are going for CPLDs, you however
may want to check out a "lower" language like ABEL. It's e.g. included in
the free Synario descendant offered by Lattice. It also comes with
schematric entry.
However, schematic entry tempts people to use asynchronous design tricks
which work(ed) with slow TTL but will most likely break on programmable
logic for various reasons, e.g. the chip's just to fast, the signal path
timing is not predictable (at least w/o digging deeper into floorplanning
and routing), or the compiler just optimizes the "redundant" logic away.
The back then common trick to delay a signal by routing it through a
series of NAND gates would be a candidate for the second case; delaying a
clock signal and XORing the delayed one with the original to get a clock
with double speed is also something which wouldn't work out of the box.
> It will be a hard task anyway to find the 65816.... I´m afraid that due
> to not finding this chip i´ll have to use the 65C02, but without it, it
> will only be half the fun... :-((
Reading the thread I wonder if it wouldn't be easier to re-design the C64
main board from scratch using a CPLD or FPGA as the one and only glue
logic (including the processor port), cache SRAM for memory and keep just
SID/VIC/CIA and the CPU of choice (either 6502, 65C02 or 65816).
With a multi-CPU setup the thing could be 100% compatible, so that you can
either switch between 1 and 2MHz while maintaining complete compatibility
and faster modes with limited compatibility (65C02 or 65816).
(Anybody ever tried clocking a 1MHz 6502 to 4MHz with appropriate cooling?
Now that people got used to that entire set of turbines inside their
computers...)
Rainer
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