From: Spiro Trikaliotis (ml-cbmhackers_at_trikaliotis.net)
Date: 2005-04-23 18:45:58
Hello,
it has been long since this post, but anyway:
* On Fri, Apr 08, 2005 at 01:19:30PM +0200 fachat wrote:
> On Thu, Apr 07, 2005 at 08:09:29PM +0200, Patrycjusz R. ??ogiewa wrote:
> > Does anyone know what function has the PCR (mapped at $1C0C) of VIA2
> > inside 1541?
[...]
> IIRC VIA2 is the drive controller VIA, so, the PCR controls the lines
>
> CB1 - not connected
> CB2 = MODE -> Output Enable (OE) of Gate Array
> CA1 = BYTE -> Gate Array Pin BYTE, also connected to S.O. of the 6502
> CA2 = SOE -> Gate Array Pin SOE
>
> IIRC MODE determines whether data is written to or read from the
> drive head, BYTE is an input that determines whether the read or
> write of a byte is finished. And SOE I cannot remember.
SOE ("Set Overflow Enable"?) is set to enable the generation of the byte
ready signal. If SOE is low, the byte ready signal will not be available
at CA1, nor will it set the overflow flag of the 6502 (via S.O. bit).
Regards,
Spiro.
--
Spiro R. Trikaliotis
http://www.trikaliotis.net/
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