From: Baltissen, GJPAA (Ruud) (ruud.baltissen_at_abp.nl)
Date: 2005-10-14 08:16:36
Hallo allemaal,
Rather annoying by filling up your email boxes, I'll combine answering
Gideons reply with a question I have: I need to switch an input between two
outputs, a 1-to-2 demultiplexer. The 74x139 is its 2-to-4 equivalent.
Anybody knows such a IC?
Hallo Gideon,
Remark: this part has to be read with a fixed font.
> Using the 8 MHz clock ....
I already have a solution (at least I think) and that ones involves the 8
MHz signal as well. I'm going to use two of those delay-IC's, the ones you
could find on XT motherboards.
For those who don't know what kind of IC this is: this IC has one input and
several outputs. The signal presented to the input appears at every output
but every time after a certain delay. The dealy for every output varies for
every model.
The first one is fed by Phi1 and, after some modifying, generates RAS, MUX
and CAS needed for a normal read or write access of the DRAMs when Phi2 =
(H).
The 8 MHz signal is fed to 74LS74 first to generate an out of phase 4 Mhz
signal at the /Q output. The Phi1 signal is fed to the CLR input causing the
/Q output to remain (H) during Phi2 = (H). If the phase of the 8 MHz signal
is not like the figure below, it has to be fed through an invertor first. A
shifted flank is not a problem.
__ _____
Phi2 : |_______________________|
__ __ __ __ __ __
8 MHZ: |__| |__| |__| |__| |__|
_____ _____ ________
4 MHZ: |_____| |_____|
______ ______ ________
CAS : |____| |____|
_______ _______ ________
RAS : |___| |___|
The above 4 MHz signal is fed to the second Delay IC and after some
modifying a CAS and a RAS are generated, a CAS-before-RAS in this case as
you can see. These and the above signals are combined using AND gates and
fed to the used DRAMs.
--
___
/ __|__
/ / |_/ Groetjes, Ruud
\ \__|_\
\___| URL: Ruud.C64.org
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