Hallo Michał, > but they are not refreshed? Just an idea: it is possible that something goes wrong during the refresh. DRAM is read/written by first negating RAS and then CAS (plus offering a part of the address of course). Refreshing is done by only negating RAS. Imagine that something goes wrong during the refresh and CAS is activated as well for one or another weird reason? $A1 end $21 have 7 bits in common; exactly the number of address lines of a 4116 DRAM. -- ___ / __|__ / / |_/ Groetjes, Ruud Baltissen \ \__|_\ \___| http://Ruud.C64.org Message was sent through the cbm-hackers mailing listReceived on 2011-01-24 22:00:14
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