Re: 264 Series and their chips

On 08/14/2011 08:20 PM, Bil Herd wrote:
> Ah, forgot about the speed, we didn't kick that on till later in the
> design cycle.
>
> I would think that the 75/85 versions should work at double clock as in
> many ways it's access times are already running at that speed, it will
> also depend on supporting  chips speeds to some degree too I think  , I.E.
> 150ns DRAMs would help, etc.  I would think that one of the problematic
> areas would be getting the address out and through the MUX/257's in time
> for /RAS, and the R/W line in time for /WE to be valid for a  clean write.

If you can still find 41464 RAMs, they are mostly from old VGA cards and 
those usually use 120ns and faster. So RAM speed shouldn't be a problem.

Another way would be to do what I did with a C64, replace the DRAMs with 
a 128Kx8 SRAM. In the C64 the VIC supplies multiplexed addresses already 
so I had to demultiplex them with a 74HCT573 first and use _RAS or'ed 
with _CAS as chip select for the RAM. Since TED doesn't supply 
multiplexed addresses and _CAS is not routed through the PLA the whole 
setup should be way easier, possibly needs only _CAS as chip select.

Currently I don't have a spare 8500 to try this with though.

Do you happen to remember the difference between the 8501R1 and the 
8501R4? I couldn't find any information concerning what was changed 
between R1 and R4.

  Gerrit



>
> Bil
>
> -----Original Message-----
> From: owner-cbm-hackers@musoftware.de
> [mailto:owner-cbm-hackers@musoftware.de] On Behalf Of Gerrit Heitsch
> Sent: Sunday, August 14, 2011 1:45 PM
> To: cbm-hackers@musoftware.de
> Subject: Re: 264 Series and their chips
>
> On 08/14/2011 07:17 PM, Bil Herd wrote:
>> We made the original 7501/8501 with a 6510 and a 74ls74 on a small
>> tower, there wasn't a dependency on the excat mapping of the I/O p[ort
>> at the time, but should be something you can put together.
>
> Even if the difference between I/O-Ports (6510 = P0-P5 and 7501 =
> P0-P4,P6-P7) can be worked around (patching all KERNAL locations and
> ignoring tape functions), the question is, will the 6510 or the 8500 work
> with 1.77 MHz the 8501 runs at part or all of the time? I don't remember
> ever seeing a 6510A and the 6510T from the 1551 which supposedly runs on
> 2MHz seems to be even more rare than a 8501.
>
> BTW: In a PAL 264 system, you can push the CPU to 2.2MHz by setting TED to
> 'display off' and 'NTSC'. You don't get usable video output, but double
> speed compared to normal. Never crashed on me, but I always had heatsinks
> on TED and CPU back then.
>
>
>
>>
>> Bil Herd
>>
>> -----Original Message-----
>> From: owner-cbm-hackers@musoftware.de
>> [mailto:owner-cbm-hackers@musoftware.de] On Behalf Of
>> Ruud@Baltissen.org
>> Sent: Saturday, August 13, 2011 12:23 PM
>> To: cbm-hackers@musoftware.de
>> Subject: Re: 264 Series and their chips
>>
>> Hallo Gerrit,
>>
>>
>> Have you ever thought about replacing the 8501 with a 8502 from a
>> C128? So far I found four differences:
>> - the 8501 has this MUX input (or output? I have no idea what it
>> does) which the C128 lacks
>> - the 8502 has an "extra" NMI input compared to the 8501
>> - the 8501 lacks the P5 I/O pin, the 8502 P7
>> - pinout doesn't match
>> If the MUX gate doesn't spoil things, what about using the 8502?
>> Regarding P5/P7: you either don't use the cassette recorder anymore or
>> adjust the bits of the Kernal.
>>
>> Just my two cents...
>>
>>
>> --
>>       ___
>>      / __|__
>>     / /  |_/     Groetjes, Ruud Baltissen
>>     \ \__|_\
>>      \___|       http://Ruud.C64.org
>>
>>
>>
>>
>>
>>
>>
>>          Message was sent through the cbm-hackers mailing list
>>
>>          Message was sent through the cbm-hackers mailing list
>>
>>
>
>
>         Message was sent through the cbm-hackers mailing list
>
>         Message was sent through the cbm-hackers mailing list
>
>


       Message was sent through the cbm-hackers mailing list