On 2013-04-08, at 22:53, Gerrit Heitsch wrote: >>>>>> If you tristate the cpu, you still have half the cycle left for the >>>>>> write. Not much more difficult. >>>>> >>>>> You also need to monitor the BA (RDY) line, otherwise you'll run into trouble when the VIC does a badline and uses the complete cycle. >>>> >>>> But - generally - if this is done on power-up, then it could possibly be done before VIC gets initialised (I assume - maybe wrong now - that it powers up with "screen disabled" state)? >>> >>> It will still do its own read cycles even if they're dummy cycles, including the refresh cycles. You might be able to get rid of the badlines though. >> >> That's what I meant. Clearing the "screen disable" bit (bit 4 at SCROLY register) is the soft way to get rid of bad lines, used in many timing critical operations. If this bit is (as I expect) cleared on power-up then at least the bad lines are not interfering and there would be no need to monitor the extra line. > > Problem is, only a power down will get VIC into that state. Just a normal RESET will not. That's exactly the case here. We (out of list) are discussing the options how to make my long-wished ultimate ROM replacement, which is to be triggered only on power-up. > So how do you make sure that the extra circuit only accesses memory after a power cycle (that is long enough to really reset VIC) but not after a user pushes the RESET button? This is not in the use cases ;-) In any case - I am neither the author, nor an ardent supporter of this RAM based approach. But just in case it would be chosen in the end, this may work on power-up, which is all what is needed here. -- SD! Message was sent through the cbm-hackers mailing listReceived on 2013-04-08 22:00:42
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