Re: Help with GAL needed

Hi,

yesterday, I was playing with my fpga board,
so I tried to write some vhd from your schematics

xilinx ise and  lattice isplever classic project in this file: 
http://www.cbm8000.com/rb.zip

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

     ENTITY rb IS
         PORT (
             clk  : in  STD_LOGIC;
             rdy  : in  STD_LOGIC;
             clk0 : out  STD_LOGIC);
     END rb;

architecture Behavioral of rb is
     SIGNAL rdy_n       : std_logic;
     SIGNAL clk_n       : std_logic;
     SIGNAL rdy_n_x_clk : std_logic;
     SIGNAL rdy_x_clk   : std_logic;
     SIGNAL f1          : std_logic;
     SIGNAL f2          : std_logic;

BEGIN
     clk_n       <= not clk;
     rdy_n       <= not rdy;
     rdy_n_x_clk <= not (rdy_n and clk);
     rdy_x_clk   <= not (rdy and clk);
     f1          <= not (rdy_n_x_clk and f2);
     f2          <= not (rdy_x_clk and f1);
     clk0        <= not (clk_n and f2);
END Behavioral;

it produced something apparently working
check rb.jpg in the zip file it's what I get on the logic analyser.

I also tried on lattice isplever classic,
it compile without errors but I dont think it produced something usable...


On 18/04/2013 09:07, Baltissen wrote:
> Hallo allemaal,
>   
>   
> I have programmed several GALs so far but they all contained only lineair equations. I have designed a WAIT circuit for the 65816, which works fine, that is built using TTL gates: http://www.baltissen.org/images/65816rdy.png
> As you can see, this schematic contains a flipflop. I use the 'old' CUPL.EXE to compile my equations. Please have a look at my equations for this schematic:
>
>
> 	Name		ISA bus with 65816, GAL #3b;
> 	Device	G16V8AS;
> 	Designer	Ruud Baltissen;
> 	Date		2013-04-18;
> 	Revision	V0.1;
>
> 	Assembly	--;
> 	Company 	--;
> 	Location	--;
> 	Partno 	--;
>
>      
> /* Define Logic Operators */
> 	/* AND = &  */
> 	/* OR = #   */
> 	/* NOT = !  */
>
>
> /* Define Input Pins */
> 	pin  2 = CLK;
> 	pin  3 = RDY;
>
> /* Define Output Pins */
> 	pin 12 = PHI0;		/* regulated CLK */
> 	pin 13 = FF1;
> 	pin 14 = FF2;
>
> /* Boolean Equations */
> 	FF1  = !(!(!RDY & CLK) & FF2);
> 	FF2  = !(!(RDY & CLK) & FF1);
> 	PHI0 = !(!CLK & FF2);
> 	
>
> CUPL compiled without any problem. But does it mean the above is good? I know it can be optimised/simplified, but as you can see the equations are a literally translation of the hardware. One part can be replaced by a single OR gate but then I would need at least three ICs in real life, now only two.
>
> As you can see I reserved output pins for the flipflop. IMHO it cannot be done in another way. But I hope to be wrong in this case; the less output pins I need, the better.
>
> Then there is the CLK input at pin 1. IMHO you only need it if you program (a part of) the GAL as counter. I know I haven't used any of the internal registers, but I don't know what CUPL made of it. So I'm not sure yet if it is needed.
>
> Any help, suggestion, etc. is surely appreciated!
>
>
> --
>       ___
>      / __|__
>     / /  |_/     Groetjes, Ruud
>     \ \__|_\
>      \___|       http://www.baltissen.org
>
>
>   
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