Hello Ruud, >>> FF1 = !(!(!RDY & CLK) & FF2); >>> FF2 = !(!(RDY & CLK) & FF1); > > When using A # B = !(!A & !B) or A # !B = !(!A & B) then you get > indeed: That the De Morgan rule. You can use it to normalize any term. >> FF1 = (!RDY & CLK) # !FF2; >> FF2 = ( RDY & CLK) # !FF1; > > But translating your result into hardware would mean I would end up > with more, and only partly used, ICs. See later. What do you meed with "translating into hardware"? You build it with discret logic elements or with an pld? That are two different things! >> PHI0 = CLK # FF2; > > But PHI0 = !(!CLK & FF2) would become PHI0 = CLK # !FF2 IMHO. You are right. My mistake. I've forgot a negation! > Unless > you meant PHI0 = CLK # FF1 because FF1 is always !FF2 in this > particular design. No! But you can do it. So you must generate the equalation for FF1 and not FF2! >> FF2 = (RDY & CLK) # (RDY & FF2) # (!CLK & FF2); > > It took me several minutes to get the same result. But what > impresses me is that you showed me that I only need one output > instead of two! Yes, you are right. It's useful for state machines. So you can reduce the feedback bits. But for asynchron states you must check for hazards. Only one bit can be changed at the same time. But you use only one bit. So this condition is always true. On the other side, if you change the schematic you can see this one feedback: +----------+ +-|\ | | o--|\ | /Reset---|/ | o-+-- Out /Set --------|/ > But my problem is my way of thinking: I'm focussed on ending up with > as less ICs as possible. Using GALs it means I have to change that > attitude. That's true. If you use discret logic elements you can choice all combination of gatter and wires. If you use pld you have a predetermined product term. This one you must use and build you equalation. So it's the best way to normalize the equalation. In higher programing languages this optimize is done automatically. Martin Message was sent through the cbm-hackers mailing listReceived on 2013-04-20 12:00:04
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