Re: My ColourPET Project

Martin,
 
I hadn't considered the shift register. That makes sense.  I see that both latches are already latched by the /LOADSR and CLK1B (via UD1), and the Shift Register also by /LOADSR. 
I'm trying to follow you... which line is responsible for delaying the Shift Register? Is it the CLK1B (via UE4)?
 
Steve


>________________________________
> From: Martin Hoffmann-Vetter <martinHV@arcor.de>
>To: cbm-hackers@musoftware.de 
>Sent: Thursday, May 2, 2013 11:59:43 AM
>Subject: RE: My ColourPET Project
>  
>
>Hello Steve,
>
>> For colour ram make sure that J7 and J8 are NOT connected (J7 is
>> normally connected for 40 column - that is the BA0 line).
>> I just tried poking $D400 (33792)  and it is active, but not
>> appearing onscreen, so we are dealing with a full character offset,
>> not just 1 or 2 pixels.
>
>After a short time of thinking, this is by design. The character data and
>the color data were readed at the same time. But the character data goes to
>the character rom and is stored in the shift register. But this is done one
>character cycle later. So you must delayed the color data, too. This is done
>with the Disp Ena from the CRTC, too. After the shift register is another
>delay. The output is latched with a d flip flop to merge it with the reverse
>bit from the video ram. (This reverse bit is delayed with d flip flops.)
>
>So i would say, the color data is 10 pixel to early. You must insert a 8 bit
>latch and synchronize it with the load sr signal. After that it must be
>delayed by one pixel. Or you use the video signal before the last d flip
>flop and extend this flip flop for your rgbi data. So you need only 4 bit.
>
>Martin
>
>
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