On 7/18/2014 5:17 PM, Segher Boessenkool wrote: > Or you read from f800..ffff and you don't need any compare ;-) Yep, I agree. My 6502 ASM-fu is not that strong. > It's the same as any other BRK, except the stack writes are turned into reads. > Seven cycles total; first three are accessing the stack, next two are > accessing the reset vector, last two are fetching the next instruction. > Depending on how you count and on how your phases are aligned etc. you'll > need to add some cycles at the start, e.g. for fetching the 2nd opcode byte. > There is also a cycle or so delay from taking the reset pin high to the BRK > being forced. And the 6500 perhaps adds extra delay from its special reset > circuitry, who knows. But I doubt it. > > So sim it on visual6502 and find out ;-) It looks like the four cycles > are exactly what it takes to get to the vector reads. But, I use 4 cycles from RESET to code execution. I figured 7 cycles, but the system responds all the way down to 4. Maybe if there was a code sequence I could use to see when it truly responds to code. The initial code is: 0xA9 0xa9 0x85 0x00 0 But, if it didn't recognize the first 3 cycles, it would do: 0 0 a9 00 85 01 . . . That seems like it would fail. Jim Message was sent through the cbm-hackers mailing listReceived on 2014-07-19 01:02:42
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