Re: ROM Dump of Amiga Keyboard controller

On 2014-07-18 21:33, Gerrit Heitsch wrote:

>> How I understood it, is that this internal clock, which is the one
>> actually dictating the CPU's actions (fetching opcodes/data), might be
>> oddly phased in regards to the supplied one. This could theoretically
>> lead to a situation when we /think/ we supply the data to the port
>> using the correct timing but in reality it happens to be improperly
>> timed, like too late for example.. ?
> 
> Lets see...
> 
>                      1    2     3     4     5
>                     __    __    __    __    __
> External clock:  __|  |__|  |__|  |__|  |__|  |__
> 
>                     _____       _____       _____
> CPU clock     :  __|     |_____|     |_____|     |
> 
> 
> You only know the external clock, but not the phase difference to the
> internal one. So when do you supply a new byte? At 1, 3, 5 or at 2 and
> 4? Rising edge, falling edge or the middle of the stable period? The
> divider is probably just a simple flipflop so the phase shift should be
> minimal.

Yes, we don't expect it to be still down when the external one goes down
for sure. But this is an assumption only of course.

> As long as you do it in a way that the date is stable when the CPU
> samples it (falling edge of its clock/PHI2 if I remember right),
> everything will work and the exact timing is not relevant as long as the
> time between command bytes is 2 periods of the external clock. So safe
> points are rising and falling edge of 1, 3, 5 and falling edge of 2 and
> 4. The rising edge of 2 and 4 would be the problematic part where the
> data might not be stable. The safest way would be in the middle of the
> HIGH or LOW portion of the external clock, that should always work.
> Together with the rather slow clockspeed supplied (250 KHz external
> clock?), it should be stable at the sampling moment.
> 
> Does that make sense to you?

Yes, and judging from this, it still doesn't change the picture much:
you can't do it just about any time. You have to give some time for the
lines to stabilise and not knowing the phase shift you can
(theoretically at least) hit the wrong moment. The fact that it all
works very well without taking too much care about the timing is most
probably because the first assumption is correct and the shift is indeed
negligible.

-- 
SD!

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