On 2014-07-20 at 08:29:47, Jim Brain (brain@jbrain.com) wrote: > > But inside the "loader" code loop you have two additional toggles > > between TEST and NORMAL mode with "extra cycle" inbetween. What was > > this needed for? If I understand correctly - the 6500 should be able > > to *store* to its RAM while running in TEST mode, shouldn't it? > The extra cycle is the dummy cycle when the sta actually happens. I > took the TEST_OFF and TEST_ON out of the code, it stopped working. > > I can't say for certain, but it would seem like only registers can be > written when test mode is high. > > That seems strange. That seems strange, indeed. $85 is a three cycles command. I take first fetches the opcode, second the operand and third should allow to execute it (it is when "sta actually happens"). Right? Have you tried to STA somewhere where you could see the result? Like another port for example? Can it be that the fact that you send_data($00) (instead of the last operand again - like send_data($00+i)) be triggerring some of those theoretical timing issues we just spoke about? -- SD! Message was sent through the cbm-hackers mailing listReceived on 2014-07-20 15:00:03
Archive generated by hypermail 2.2.0.