> On 2016-01-22, at 15:38, Gerrit Heitsch <gerrit@laosinh.s.bawue.de> wrote: >>> >>> Remember that VIC will still use the bus though, only the CPU is taken offline with the DMA line! So you have only about 500ns time before you need to free the bus again. >> >> Sure. You'd need to act the way CPU does - use "half-cycles". > > There is another problem with the DMA line. It affects AEC and RDY. But the 6510 cannot be stopped in a write cycle. That's why the VIC sets RDY 3 cycles earlier than it needs the bus (3 write cycles in a row is the max that can happen). > > That means you cannot use the DMA signal for accessing Memory while the 6510 is doing something useful. Sooner or later you will assert it while the CPU is in a write cycle and cause data corruption. Can't you HLT it first? In any case - as written already - if only PEEKing the locations is needed, then this isn't even needed at all. -- SD! Message was sent through the cbm-hackers mailing listReceived on 2016-01-22 15:01:10
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