Re: FPGATED

From: Gerrit Heitsch <*gerrit_at_laosinh.s.bawue.de*> Date: Sat, 23 Jul 2016 21:16:18 +0200 Message-ID: <5793C282.8070705@laosinh.s.bawue.de> · gerrit_at_laosinh.s.bawue.de

On 07/23/2016 09:08 PM, Segher Boessenkool wrote:
> On Sat, Jul 23, 2016 at 08:46:04PM +0200, Gerrit Heitsch wrote:
>> On 07/23/2016 08:22 PM, Segher Boessenkool wrote:
>>> On Sat, Jul 23, 2016 at 06:29:33PM +0200, Michał Pleban wrote:
>>>>> Next project would be a replacement 8501 since those also die easily...
>>>>
>>>> That should be much easier, as no analog stuff (video) is needed and a
>>>> 6502 core is easily obtainable... Somebody should really make such
>>>> project :-)
>>>
>>> The visual6502 project has a die picture of an 8501.  From the picture
>>> it seems clear that both the 8500 (c64c) and 8502 (c128) used the same
>>> silicon, with different contacts bonded out.
>>
>> You sure? The 8501 is missing Port-Bit 5. It's not only not bonded out,
>> it's not present, you can't set it while the 8500 has all the port bits,
>> you can set them.
>
> (bit 5?  Do you mean bit 7?)

No, the 8501 is missing Bit 5, Bit 6 and 7 are present and used. They 
are used as inputs from the IEC bus. I assume since that makes is easy 
to use the BIT command or ROL/ASL for serial/parallel conversion.

> Why do you think you can set all port bits on the 8500?

Because people have been trying to use Bit 6 and 7 to determine CPU 
temperature or detecting a 6510 or 8500 from the time it takes a 1 to 
become a 0 when switching the port from output to input.

  Gerrit

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