> Hello! > > I read the 6703 PLA in an EPROM reader and minimized the equations. On a > first glance they look good - the appropriate chips are selected in > correct places on CPU and VIC accesses (note that RW_IN is negated and > delayed with regard to CPU RW signal): > > (1) nRAM = A11 > or A12 > or A13 > or A14 and BA and CLK0 > or A14 and CLK0 and RW_IN > or A15 and BA and CLK0 > or A15 and CLK0 and RW_IN; > > (2) nEXRAM = A12 > or A13 > or A14 and BA and CLK0 > or A14 and CLK0 and RW_IN > or A15 and BA and CLK0 > or A15 and CLK0 and RW_IN > or not A11; > > (3) nROML = A13 > or A14 > or not A15 > or not BA and not RW_IN > or not CLK0; > > (4) nVIC = A10 > or A11 > or A13 > or not A12 > or not A14 > or not A15 > or not CLK0; > > (5) nSID = A11 > or A13 > or not A10 > or not A12 > or not A14 > or not A15 > or not BA and not RW_IN > or not CLK0; > > (6) nCOLRAM = A10 and BA > or A10 and RW_IN > or A13 and BA > or A13 and RW_IN > or not A11 and BA > or not A11 and RW_IN > or not A12 and BA > or not A12 and RW_IN > or not A14 and BA > or not A14 and RW_IN > or not A15 and BA > or not A15 and RW_IN > or not CLK0; > > (7) nCIA = A13 > or not A10 > or not A11 > or not A12 > or not A14 > or not A15 > or not CLK0; > > (8) nROMH = not A12 and not BA and not RW_IN > or not A12 and not CLK0 > or not A13 > or not A14 and BA and CLK0 > or not A14 and CLK0 and RW_IN > or not A15 and BA and CLK0 > or not A15 and CLK0 and RW_IN; > > (9) RW_OUT = not BA and not RW_IN > or not CLK0; > Hello Michau, So you were able to read your dead one, or it wasn't dead, or you got another? -Pete Message was sent through the cbm-hackers mailing listReceived on 2016-08-05 21:00:08
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