On Fri, Aug 05, 2016 at 08:30:48PM +0200, Michał Pleban wrote: > Hello! > > I read the 6703 PLA in an EPROM reader and minimized the equations. On a > first glance they look good - the appropriate chips are selected in > correct places on CPU and VIC accesses (note that RW_IN is negated and > delayed with regard to CPU RW signal): That gives: === T := (BA or RW_IN) and CLK0 if (T) { not #RAM := A15..A11=00000 not #EXRAM := A15..A11=00001 not #ROML := A15..A13=100 not #ROMH := A15..A13=111 } else { not #RAM := A13..A11=000 not #EXRAM := A13..A11=001 not #ROML := 0 not #ROMH := A13..A12=11 } not #VIC := A15..A10=110100 and CLK0 not #SID := A15..A10=110101 and T not #COLRAM := (A15..A10=110110 or not T) and CLK0 not #CIA := A15..A10=110111 and CLK0 RW_OUT := not T === The memory part makes perfect sense, but the rest is a bit weird. Segher Message was sent through the cbm-hackers mailing listReceived on 2016-08-06 01:00:13
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