Re: MAX Machine PLA equations

From: Michał Pleban <*lists_at_michau.name*> Date: Sat, 06 Aug 2016 13:30:20 +0200 Message-ID: <57A5CA4C.9070101@michau.name> · lists_at_michau.name

Hello!

Segher Boessenkool wrote:

> The I/O part becomes
>  [...]
> which seems sane, except for the VIC accesses to VIC and CIA.  

Yes, that got my attention too. Looking at the Excel with the truth
table, it is evident that nVIC and nCIA are driven in the VIC address
space where it does not make any sense. Maybe it's some kind of error
the designers made, and nobody noticed (or nobody bothered)?

> What drives A15,A14 during such accesses, anyway?

Good question. I can't see anything in the schematic that could drive
them. Maybe that's not very relevant, since the VIC memory map seems to
repeat itself every 16 kB.

Regards,
Michau.

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