On 08/07/2016 09:23 PM, Segher Boessenkool wrote: > On Sun, Aug 07, 2016 at 02:38:09PM +0200, Gerrit Heitsch wrote: >> On 07/31/2016 04:48 PM, Segher Boessenkool wrote: >>> Same with VIC-II: the 6566 is a very nice and clean design (what I can >>> reconstruct from it anyway, I haven't seen an actual die photo)... The >>> DRAM versions, not so very clean. >> >> The interesting part would be to compare the 6566 and 6567 dies to see >> what was changed and how much is the same. Where did they squeeze in the >> refresh counter, the RAS/CAS logic, were things moved around for it... > > http://segher.ircgeeks.net/vic-ii/8565-blocks.jpg > > (that is 8565, not *entirely* the same as 6567/6569, but I labeled the > blocks here). > > This is 6569 (R3): > > http://retronn.de/imports/cbm_chips/vic2_overview_gray4.jpg > > and this is R1 (warning, huge): > > http://mail.lipsia.de/~enigma/vic2r1/fullvic_lowquality.jpg > > (not much has changed in R3). Likely some timing issues. > Refresh counter sits next to the VM counters (it also writes the low > address bits, and the VM counters were handily on the end of things > already). > > Here's a piece of the pinout, including all changed signals: > > 6566 6567 > 17 phi0 phi0 > 18 phiin #RAS > 19 phicol #CAS > 20 Vss Vss > 21 A0 phicol > 22 A1 phiin > 23 A2 A11 > 24 A3 A0/A7/A8 > 25 A4 A1/A8/A9 > 26 A5 A2/A9/A10 > 27 A6 A3/A10/A11 > 28 A7 A4/A11/A12 > 29 A8 A5/A12/A13 > 30 A9 A6/A13/1 > 31 A10 A7 > 32 A11 A8 > 33 A12 A9 > 34 A13 A10 Hm? What do you mean with the 3 Adress lines on a single pin of the 6567? The schematics of the C64 only show 2 per adress line. > Btw, the RAS/CAS things are self-timed, using analogue delays, long > inverter chains etc. There should be differences between R1 and R3 in this area since R1 wants a 82pF Capacitor between CAS and GND while it's not needed for R3. Gerrit Message was sent through the cbm-hackers mailing listReceived on 2016-08-07 20:00:35
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