On 12/10/2016 07:36, Baltissen, GJPAA (Ruud) wrote: > Hmm, I got interrupted while writing this and forgot about it. So: > But the 414256 (256K*4) does need 9 refresh cycles. The problem of the C64/128: how to add that extra cycle? Otherwise one could have used SIMM modules instead of single ICs. > > IIRC adding extra cycles to a CBM is just a matter of piggybacking another counter. But, just popped up in my mind, IMHO unnecessary because I have some SMD 512 KB SRAMs laying around: > - no refresh problems > - no cutting of wires etc., etc. > I will work it out if I have some time.... Could your counter tell the difference between a dram access and a dram refresh though? Static ram is obviously a whole lot easier, once you de-multiplex the address lines (or if you can bypass the multiplexing). On a c64 that should also give you the advantage of being able to avoid the VSP memory corruption. Message was sent through the cbm-hackers mailing listReceived on 2016-10-12 14:00:02
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